This invention relates to electronic test systems for testing microprocessor based circuits. In particular, the invention relates to electronic test systems having a interface device for providing a test connection on a circuit under test at a location remote from microprocessor and memory devices.
Electronic test systems are frequently used in the development, manufacture and repair of electronic circuits. In a simple electronic test system, one or more test signals are applied to a unit under test (UUT) and the response of the unit is measured at one or more locations. Potential faults may be identified by comparing the responses obtained from the circuit under test with those of an ideally functioning circuit. For testing microprocessor systems, a number of methods are available. These methods include:
1. xe2x80x9cScope and grope testingxe2x80x9d,
2. ROM (Read Only Memory) emulation,
3. Microprocessor emulation using cycle stealing, and
4. Microprocessor testing using the debug port of the processor.
In xe2x80x9cscope and gropexe2x80x9d testing, a technician determines the location or nature of a fault using one or more of a multiplicity of techniques, including for example continuity testing. In doing so, the technician isolates problems or faults using a combination of skill, experience, persistence and luck, but without the assistance of any automated testing. Particularly with complex boards such as microprocessor baseboards, this type of testing is time consuming, requires experienced technicians and, in most situations, is uneconomic.
With ROM emulation, the boot-up ROM is replaced by a ROM emulator circuit. The boot-up ROM contains the initialising program to be run by a microprocessor each time it is switched on or reset. The ROM emulation circuit also provides a microprocessor with a program, but the program is designed as a diagnostic program rather than as a strict initialising program. Responses of the microprocessor and circuit to this program can be measured at various locations in the circuit. Typically, these ROM emulation circuits return test result information through the emulation circuit. This test information is processed by a computer for viewing on screen or for automatic highlighting of potential failures.
EP-A-0,191,632 describes the use of a method for returning data through the emulation circuit, wherein logic circuitry in the ROM emulator permits test data to be read over the system address bus (the data bus cannot be used in this instance since data cannot be written to a ROM device). If the area of the circuit under test between the microprocessor and the boot ROM is defective, then ROM emulation will not work.
U.S. Pat. No. 4,622,647 discloses a gripper for use in conjunction with ROM emulation circuits. The gripper is connectable to a microprocessor and permits measurement of logic signals at the terminals of the microprocessor. This method does not necessarily rely on a diagnostic program in the ROM emulation circuit to return data, but typically does require such a program in order to run a test. The method described provides reliable data only from the microprocessor. The reliability of data from other locations relies on the integrity of components and connections, while in addition, the reliability of gripper connections is typically not high and false indications of errors are likely to occur frequently due to bad connections.
In microprocessor emulation using cycle stealing, as described in EP-A-0,067,510, the microprocessor in the circuit under test is replaced by a test circuit containing a similar microprocessor. To achieve this, the circuit microprocessor must be removed or disabled. Where a socket has been used to house the microprocessor, this is a simple matter. However, more commonly, microprocessors are soldered onto boards and with pin counts often of the order of several hundred, the removal of a microprocessor becomes difficult. Some chips permit an alternative method of disabling a chip by switching a particular input to a specific state. Typically this is achieved by placing a test clip over the processor. During testing, the test device interrupts the unit under test, injects a read or write cycle, collects the result, and then removes itself (logically not physically) from the buses of the unit under test. In addition, where the microprocessor has been disabled, rather than removed, a gripper or similar feature must be connected on top of the processor so as to connect with all the pins on the microprocessor. This is a troublesome method, and frequently failures will be highlighted by the test system arising not from a fault in the circuit under test but from a faulty connection between the gripper and microprocessor. A further disadvantage of these microprocessor emulation systems is that the microprocessors must be removed from the units under test or disabled. As a result, a key element of the circuit is not being tested.
Microprocessor testing using the debug port is a method only available for use with certain types of microprocessors, i.e. those that have a debug port. In this method, the test system connects directly to the processor in the unit under test via the processors debug port. The electronic test system may connect to the debug port via either a port connector on the unit under test or an interposer card which sits between the processor and its socket. An advantage of this method is that the test system need only connect to a small number of pins on the microprocessor. Accordingly the possibility of an error arising from a poor connection with the test system is reduced.
Using the above mentioned microprocessor testing methods, a variety of tests may be performed on a system, examples of which include BUS tests, ROM tests and DRAM tests. A significant disadvantage of the above test systems is that they can only test the circuits under test at the location of the ROM or processor. Other areas of the circuit cannot be tested directly.
Irish Patent Application No. 1576/89 discloses the use of a probe with a ROM emulation system. The probe enables signals to be detected at various locations around a circuit and returned for display on a computer system along with the results of the ROM emulation circuit. Thus faults can be localised, once they have been highlighted by s another test method. In testing, the probe may be positioned by hand at the correct location and repositioned as required. This is useful where a single track is faulty, and the probe is used to find that track or the location on a track of a fault.
Modern microprocessor circuit architectures are frequently arranged in a hierarchical structure, as illustrated in FIG. 1, with different layers of the hierarchy operating at different speeds. Using the above methods, it is difficult to test the operation of such a circuit simply using one or more of the above methods. In particular, problems can arise in attempting to automatically test and diagnose the lower bus layers.
One method of testing the lower bus layers of a unit under test, using ROM or microprocessor emulation, is to write a pattern of data to an address location on a device/chip connected to a lower bus layer. If the same address location when read back returns a different pattern of data, then this indicates a fault.
One difficulty using this technique is that the test may have to be changed for each make and model of device/chip used on a board, as for example each device may have different read/write addresses. This will require a not insignificant amount of work, and reprogramming of a test system by an experienced technician.
Modern computer systems commonly feature a plug-and-play facility. This facility allows a computer to accept a variety of add-on cards/devices, e.g. sound cards, I/O chips etc., without the user having to specify the addressing and interrupt requirements for each device. Upon start-up of a computer possessing this plug-and-play facility, all the devices and cards are initially left powered down (sleep mode). The computer then powers up each device individually, determines that device""s addressing and interrupt requirements, and then powers it down. Once the microprocessor has determined all of the attached devices requirements, it assigns addresses and interrupts to each device, ensuring there are no conflicts. The individual devices are then powered up and normal operation of the computer commences.
This plug-and-play facility can cause problems when attempting to test buses remote from the microprocessor. In particular, when using the above mentioned method of writing a data byte and then reading it back from a device, the device may not power up because of a fault either in the device or on the bus. As a result, a technician will have t o use a probe or other means to isolate the fault, which is time consuming.
The se shortcomings and others are addressed and substantially overcome by the present invention, which provides a method and apparatus for use with an electronic test system to enable the direct testing of buses on a unit under test (UUT). More specifically, a connection and interface for an electronic test system are provided, which are simple to use, fast to connect and reliable, which may be used as an extra point of test and/or for testing buses remote from the microprocessor of a circuit under test, and which may also be used independently of any devices of the circuit under test. The test apparatus and method may be us ed to test buses remote from the microprocessor without the use of peripheral devices on the circuit under test, for example I/O chips.
In accordance with one embodiment of the invention, an interface device is provided for use with an electronic test system for testing circuits including a processor. The interface device comprises control means, first communicating means for communicating between the control means and the electronic test system, and second communicating means for communicating between the control means and a circuit under test. The control means is responsive to instructions from command means of the electronic test system to communicate data to or from the circuit under test, and the second communicating means comprises means for enabling access to a bus of the circuit under test. The bus access-enabling means preferably comprises connection means for connecting to a bus of the circuit under test, while the connection means comprises a bus slot connector. The control means may comprise a data capture circuit, and may be implemented as at least one FPGA.
In accordance with another embodiment of the invention, a method of testing an electronic circuit including a microprocessor is provided. The method comprises the steps of generating a test signal, applying the test signal to a first location of the circuit under test, and measuring the response of the circuit under test to the test signal at a location of the circuit under test different from the first location, wherein at least one of the locations enables access to a bus of the circuit under test. Preferably, the test signal is applied via a ROM emulation circuit, or, in an alternative embodiment, the test signal may be applied via a microprocessor emulation circuit.
In accordance with yet another aspect of the invention, the step of measuring the response further comprises measuring the response at connecting means for connecting to a bus of the circuit under test. The connecting means may comprise a bus slot connector. The method may further comprise processing the response for display of test results, wherein the processing of the response is implemented at least in part by at least one FPGA.
In still another form of the invention, electronic test apparatus is provided for testing an electronic circuit including a microprocessor. The electronic test apparatus comprises at least first and second means enabling access to a circuit under test, means for generating a test signal, means for applying the test signal to the first access-enabling means, and means for measuring, at the second access-enabling means, the response of the circuit under test to the test signal applied at the first access-enabling means. At least one of the access-enabling means enables access to a bus of the circuit under test.
Preferably, one of the first and second access-enabling means comprises connection means for connecting to the circuit under test. The connection means may comprise a ROM emulation circuit, or, in the alternative, a microprocessor emulation circuit. The first access-enabling means may comprise connection means, where the connection means is alternatively a ROM emulation circuit or a microprocessor emulation circuit.
In still another form of the invention, the second access-enabling means comprises connection means for connecting to a bus of the circuit under test, wherein the connection means comprises a bus slot connector. The second access-enabling means may comprise control means, which may in turn comprise a data capture circuit. The control means is preferably implemented as at least one FPGA.
Further objects, features, and advantages of the present invention will become apparent from the following description and drawings.